Responsibilities
- Lead project task force.
- Learn standard/algorithm and define the IP/SOC specification and architecture.
- IP integration, implementation, and timing closure.
- IP integration, implementation, and timing closure.
Essential Requirements
- Bachelor’s degree in Electrical Engineering or Computer Science.
- 5+ years SOC design, verification, or related work experience.
- Experience in digital IP design using Verilog or SystemVerilog.
- Experience with several chip tapeout and mass production.
- Specific experience with industry standard development tools is required.
- Solid understanding of complete SOC design flow and design techniques and methods.
Desirable Pluses
- Master’s degree in Electrical Engineering or Computer Science.
- Experience with architecture, specification definition, task force leading, project leading.
- Experience with SOC flow building.
- Experience with IP integration or SOC integration.
- Experience in one or more of the following domains, is a plus:
- High-Level Synthesis using SystemC
- Synopsys HAPS, Xilinx FPGA
- LPDDR
- AXI, AHB design
- Neural network
- Low power design
- USB, MIPI, sensor, display, peripherals
- Floorplan, package
Tagged as: SOC, systemc, systemverilog, verilog
