Responsibilities
Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.
Essential Requirements
- Familiar with Synopsys/Cadence backend design flow.
- Hand on APR physical design from netlist to DRC/LVS tapeout experience is required.
- Experienced in hierarchical implementation, low power design flow, timing closure, IR drop analysis, crosstalk analysis.
- Familiar with TCL/Perl scripting and design automation.
- Experience in 65/55nm design is must, and 28/40nm or below design is a plus.
Additional Requirements
- 3 年以上工作經歷
- 電機電子工程、資訊工程相關科系，大學以上畢業
- 英文：聽說讀寫，中等程度
