- Responsible for 40nm and 28nm BEOL process developing, failure analysis, FMEA, and Pareto-chart. Based on the results, develop a plan for process improvement accordingly.
- BEOL PCM design and collaborate with Fab for inline monitor management.
- Responsible for design of BEOL test keys incorporates complicated layouts such as via chains, stack via chains, metal snakes, and combs. Combined with electrical testing and test key layouts to improve BEOL yield.
- Collaborate with module teams for technology development, and process window improvement.
- Collaborate with reliability team for process qualification.
- Establish relevant process documents and BEOL design rule manual.
- Master’s or PhD degree in Electrical Engineering, Electronics, Physics, Materials Science, or related field.
- 10+ years of semiconductor process integration and development experience in 12-inch wafer fabs.
- Experience with Cu/damascene/PAD/passivation process development is necessary.