Role scope
- Front end digital design for delivering MemryX’s breakthrough product
- Develop and integrate design blocks
- Execute block level simulation and verification to ensure basic functionality
- Execute chip level simulation and verification and test for integration
- Run digital design flow checks– lint, LEC, synthesis, timing, etc
Requirements
- MS/PhD in EE/ECE with 3-12+ years of experience in VLSI/Embedded Systems Design
- Working experience of Verilog, System Verilog and designing blocks from scratch
- Hands-on experience and ability to master new technologies and complex systems
- Experience in bus interface design, SoC integration
- Effective English communications for cross site co-work
Nice to have
- Experience in standard interfaces protocols (USB/PCIe) and common IP blocks
- Experience in chip tape-out and volume production, especially in sub-40nm nodes
- Skilled in system verification such as FPGA prototype buildup and debug
- Familiarity with script programming such as shell script, make, Python, etc
- Startup experience, ML SoC development
技能標籤： LEC, lint, RTL, STA, synthesis, systemverilog, verilog
