工作內容
- RTL/Digital circuit design, synthesis, and simulation/verification
- FPGA synthesis, verification
- Chip integration, algorithm implementation, and interface design
- Generate test pattern
應徵條件
- Familiar with ASIC Flow / EDA Tool (Synthesis DCG , Scan at-speed insertion, LEC , CLP , PrimeTime STA , PTPX , Low power flow implement). Experience in CAD Team is a plus
- Familiar with ASIC/FPGA Integration(ARM CPU architecture , AXI / AHB / VCI Bus arbiter , Clock tree scheme , ASIC / SOC Power optimization flow, Xilinx FPGA V7 Scale)
- Familiar with high-speed NAND flash spec and control or eMMC/UFS IP design is a plus
技能標籤： asic, digital, EDA, RTL
