Job description
- Work with IC architects and designers to decide the specifications and verification plans
- Ensure functional and code coverage of complex RTL design blocks
- Work with software team to enable software development and testing
Job requirement
- BS, MS or PhD in electrical engineering, computer engineering or computer science with a special focus on digital system design and verification
- 5+ years of industry experience is preferred
- Experience in SoC or ASIC verification for at least several chip tapeout-out and volume production projects
- Familiarity with UVM, can setup a UVM test environment and create UVM models from scratch is required
- Experience in design, simulation and debug EDA tools
- Experience in RTL. Verilog and SystemVerilog are required
- Familiarity with script programming such as shell script, make, Python, etc.
- Skills in system verification such as FPGA prototype buildup and debug are desirable
- Familiar with CAD flow, can help to setup company design flow environment such as LEC/Linting/CDC/synthesis flow are preferred
- Willing to take on challenges, and effective English communications and co-work with other team members
Compensation and benefits
- Salary + bonus: NTD 1M-4M/year depends on capability
- Stock option offerings
- Generous PTO and benefits
- High growth potential
技能標籤： asic, C, fpga , github, linux, MCU, RTL, verilog
