工作內容
- SoC level and IP level verification methodology
- Develop a verification plan and Integrated verification environment
- Integrate VIP into the SOC verification platform
需求條件
- 碩士以上資訊工程、電機電子工程相關畢，5年以上相關工作經驗
- Familiar with high speed (PCIE, USB, HDMI, DP) protocol and architecture
- Knowledge and design experience in design verification, such as UVM/VMM/OVM and system Verilog / Verilog
- Scripting experience in Shell, Perl, Python
- Knowledgeable in DDR/JPEG/H.264/H.265 is a plus
技能標籤： IP, OVM, Protocol, SOC, system verilog, UVM, verification, VMM
