工作內容
- Digital IC design
- Verilog RTL coding and simulation
- ASIC front-end design flow development
- Familiar with Tessent MBIST flow integration
需求條件
- Experience in the Tessent MBIST flow is preferred.
- Familiar DFT flow: ATPG / BSD / Memory BIST
- Familiar with Verilog RTL coding/simulation and SoC integration
- Familiar with Verilog / TCL / Perl / shell script / makefile
