Responsibilities
- Digital IC design
- RTL coding / simulation
- Frontend Design Flow
- FPAG/Emulator platform
Essential Requirements
- Familiar Verilog RTL coding/ simulation
- Familiar with Design Compiler/PrimeTime/Prime Power/Conformal LEC/DFT/BSD
- Familiar with 28nm/12nm or advanced process
- Familiar with low power methdology
- Experience in FPGA verification、ATPG/BIST design is a plus.
- Experience in PCIe SSD platform is preferred.
- Experience in PCIe/NVMe/Nand is preferred.
Additional Requirements
- 3年以上工作經歷
- 電機電子工程、資訊工程相關科系，碩士以上畢業
- 英文：聽說讀寫，精通程度
技能標籤： asic, fpga , verilog
IC design 經驗約4年。
考試時間約一小時，之後主要討論過去經歷及介紹 SMI 的產品，coding 約10題都是概念題。