工作內容
- Digital IC designer
- RTL coding/simulation
- ASIC front-end design flow development
- Familiar with Physical Design EDA tools
- SOC / IP synthesis, DFT, STA and timing closure
需求條件
- Familiar with Verilog / TCL / Perl / shell script / makefile
- Familiar with Design Compiler: DCG synthesis / Floorplanning / low power flow
- Familiar DFT flow: OCC/ Scan compression / ATPG / BSD / Memory BIST
- Familiar with Prime Time: STA / PTPX / Timing closure flow
- Familiar with Conformal: LEC / CLP
- Familiar with 28nm or advanced process
- Experience in the Tessent MBIST flow is preferred
Tagged as: systemverilog, verilog
