工作內容
- Design FFE/DFE for ADC based serdes in PCIe project
- Synthesis/STA fronted flow
需求條件
- 碩士以上資訊工程、電機電子工程相關，5年以上相關工作經驗
- Familiar with FFE, DFE RTL design
- Familiar with synthesis flow
- Familiar with PAM4 serdes architecture
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