Responsibilities
- Develop the IP Verification environment by Verilog / System Verilog, such as USB 3.2 /PCI-Express/Serial ATA/MIPI IP Verification.
- Define the validation and verification plan of the high speed interface.
- Verification and debug the high speed interface.
Essential Requirements
- Familiar with high speed (PCIE, USB, MIPI, SATA) protocol and architecture.
- Knowledge and design experience of design verification such as UVM and system Verilog / Verilog.
Additional Requirements
- 3年以上工作經驗
- 電機電子工程/資訊工程/通訊學類相關科系，碩士以上畢業
Tagged as: verification, verilog
