工作內容
- RTL/Digital circuit design, synthesis, and simulation/verification
- FPGA synthesis, verification
- SOC architecture development & integration, algorithm implementation
- High speed Serdes IO design & verification
需求條件
- Familiar with complete ASIC design flow, UPF, and EDA tools (DCG synthesis, at-speed scan insertion, modern memory bist insertion and STA)
- Experience in ASIC/FPGA integration (ARM CPU architecture, AXI/APB bus protocol, Clock/Reset structure, Xilinx FPGA/HAPS implement)
- Familiar with DDR system architecture & integration or High-speed I/O protocol such as PCIe and USB
- SOC DFT and Low-power implementation experience are a plus
Tagged as: systemverilog, verilog
