Responsibilities:
- SoC architecture design with performance, power and area analysis
- Embedded CPU ( ARC, RISC-V, ARM) and on chip bus subsystem design, integration and verification
- ISP ( Image Signal Processing ) subsystem design, integration and verification
- AI NN ( Neural Network) accelerator subsystem design, integration and verification
- SoC integration and verification
- Familiar with RTL-to-GDSII design flow, FPGA prototyping and HW emulation
- Skillful in EDA front end tools ( synthesis, STA, equivalence checking, static/dynamic verification and low power UPF verification)
Tagged as: ee/ce, ic design, SOC
