工作內容
- Integrate DDR controller/phy related IPs
- Analysis design and verify DDR controller/phy
- Maintain and improve ASIC design/verification environment
- Maintain DRAM Mass Production ICs and issue Tracking/debugging
需求條件
- Familiar with SystemVerilog/UVM is a plus
- Familiar with ARM Bus Protocol is a plus
- Familiar with FE tools such as nLint/CDC/Code Coverage tool is a plus
- Familiar with perl/makefile/python language is a plus
- Effective interpersonal communication skills
Tagged as: IC, integration, IP, Protocol, RTL
