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Job description

  • Compute accelerator blocks design, SoC design and integration
  • Compute accelerator blocks, SoC and simulation and verification
  • Run all digital design flow(synthesis/STA/lint/LEC/…)

Job requirement

  • BS, MS or PhD in electrical engineering, computer engineering or computer science with a special focus on digital system design, computer architecture or computer hardware design.
  • 3~10 years of industry experience is preferred.
  • Experience in RTL design. Verilog is required and SystemVerilog is preferred.
  • Experience in ARM processor, bus design, SoC integration, standard interfaces protocols and common IP blocks.
  • Experience in design flows for simulation, synthesis, verification, design for testing, static timing analysis, logic equivalence check, etc.
  • Experience in chip tape-out and volume production, especially in sub-40nm nodes.
  • Skilled in system verification such as FPGA prototype buildup and debug.
  • Familiarity with script programming such as shell script, make, Python, etc.
  • Willing to take on challenges, and effective English communications and co-work with other team members.

Compensation and benefits

  • Salary + bonus: NTD 1.2M-3M/year
  • Stock option offerings
  • Generous PTO and benefits
  • High growth potential

Tagged as: GIT, github, linux, MCU

4 interview reviews on this position: 數位 IC 設計工程師
Please go Interview Reviews page for furthur reviews.

  1. Consultant in charge
    Reply
    The interview reviews are provided by JECHO candidates, any unauthorized reproduction is prohibited.

    碩士畢,6 年以上相關經驗,並有相關獲獎經歷。

    面試約一小時半,面試官一位,很好相處,印象很好。
    主要都在討論人選背景及進行的專案內容,剩餘時間面試官會稍微介紹公司組織,分為設計部門及驗證部門,以及公司人數。
    並提到如果有後續消息,未來面試還會有兩關,技術考試、高階主管面試。
    目前興趣度極高,並有簡單討論未來可上工時間。

  2. Consultant in charge
    Reply
    The interview reviews are provided by JECHO candidates, any unauthorized reproduction is prohibited.

    碩士畢業,12 年以上相關經歷,並有嵌入式軟、硬體開發經驗,熟悉相關背景知識。

    面試時間 1.5 小時。
    詢問過去經驗,接著面試官提出相關問題,包括 DMA、Timer Interrupt、Memory storage 等經驗,人選表示,感覺出目前比較想找專職在 firmware 的人才。面試官有提到他們是新創,氛圍比較開放但相對有些風險,對面試官印象不錯,覺得很誠懇,是會想一起工作的人。

  3. Consultant in charge
    Reply
    The interview reviews are provided by JECHO candidates, any unauthorized reproduction is prohibited.

    碩士畢業,資深數位 IC 設計師,精通高速混和模式設計,了解 5G 無線開發及 ML、DL 音頻信號處理應用。
    申請動機:對於 AI 有興趣,並對創辦人學術論文有些研究

    一面時間約 1.5 小時,討論人選履歷為主,有談到公司內部發展規劃與組織,目前美國與台灣 team 各約 10+人,美國以架構為主,台灣軟體居多。面試官表示需要與內部人員討論才會知道是否有二面。面試官對於人選高速周邊介面經驗蠻喜歡的,覺得很有潛力。

    二面會有測驗,像是實作問題,類似 verilog 解釋相關設計,並與美國團隊面試。

  4. Consultant in charge
    Reply
    The interview reviews are provided by JECHO candidates, any unauthorized reproduction is prohibited.

    碩士畢,豐富的 ASIC 設計經驗,專攻 USB、PCIe 高速介面多年。

    第一關面試約 1.5 小時,相談勝歡,討論履歷背景外,也回答了所有人選提問,包含目前產品走向、公司發展、技術、架構等等。
    目前 MemryX 的確就是需要找尋 SerDes 相關領域的人才,但是 MemryX 更讓人選有興趣的是 AI 處理核心的演算法及架構。因為職涯規劃中期待能接觸新的領域,面試官也表示這部分是可以商量,盡量在工作的內容上符合人選的期待。
    面對新創團隊的期待,人選覺得是個優勢,可以一人碰多個面向的工作模式,下一關面試將與台灣團隊與老闆。

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