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This leadership role will be in charge of the Design Verification team. It is a high visibility role that requires involvement in all aspects of team deliverables, growth and operations, including but not limited to setting verification architecture and environment, use case analysis, test content development and coverage, hiring key talent and establishing best design practices.

Role scope

  • Build, inspire, mentor and retain high-performing Design Verification engineering team responsible for delivering MemryX’s breakthrough product
  • Develop and execute block level simulation environment and verification test suite to ensure complete functionality
  • Execute chip level simulation, verification and coverage and regression
  • Develop and manage engineering handshake with design service partner
  • Collaborate with other stakeholders on discussions for product features
  • Hire industry best talent to scale the engineering organization

Requirements

  • MS/PhD in EE/ECE with 12+ years of experience in VLSI/Embedded Systems Design
  • 10+ years of hands-on experience and ability to master new technologies and complex systems
  • Proven leadership skills and track record in successfully driving technical/architectural solutions to products
  • Working experience of Verilog, System Verilog and verification of SoC and new IP blocks
  • Experience in bus interface verification and Bus Functional Models (BFM)
  • Effective English communications for cross site co-work

Requirements

  • MS/PhD in EE/ECE with 3-12+ years of experience in VLSI/Embedded Systems Design
  • Hands-on experience and ability to master new technologies and complex systems

Nice to have

  • Experience in standard interfaces protocols (USB/PCIe) and common IP blocks
  • Skilled in system verification such as FPGA prototype buildup and debug
  • Familiarity with script programming such as shell script, make, Python, etc
  • Startup experience, ML SoC development

技能標籤: design verification, ECE, EE, python, shell script, verilog

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