Responsibilities

  • PCIE IP digital design including RTL coding, verification, Synthesis, Integration, FPGA verification and chip tape out.

Essential Requirements

  • Familiar with PCIE protocol, experience on developing PCIE IP.
  • Knowledge and design experience of digital flows and FPGA validations.
  • Experience on the system level debug and issue analysis.

Additional Requirements

  • 2年以上工作經驗
  • 電機電子工程/資訊工程相關科系,碩士以上畢業
  • 英文:聽說讀寫,中等程度
  • 需出差,一年累積時間未定

Tagged as: fpga  , pcie ip, RTL

One interview review on this position: 數位 IP 設計工程師
Please go Interview Reviews page for furthur reviews.

  1. Consultant in charge
    Reply
    The interview reviews are provided by JECHO candidates, any unauthorized reproduction is prohibited.

    相關產業經驗 3 年。
    擅長:PCI Express 2.0 and PIPE interface、AMBA AXI、Design Compiler、IC Compiler、SoC Encounter 等。
    由兩位面試官進行面試,環境及文化不錯。以 IP 設計為主,聚焦在 PHY,對工作抱持期待,喜歡整體工作內容,並能學到很多東西。

Leave a Reply or a Review

*