工作經驗
- 3年以上，55/40nm design為必要條件、有28/16nm or below design 加分
- 5年以上，FinFet design為必要條件、有whole chip integration加分
工作內容
- Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout
需求條件
- Familiar with Synopsys (ICC2 or FC & PrimeTime)/Cadence (Innovus & Tempus)
- Perform netlist-to-GDSII design flow, including floorplanning, power grids, clock tree synthesis, place & route, and physical verification
- Experienced in hierarchical implementation, low power design flow, timing closure, IR drop analysis, and crosstalk analysis
3年以上工作經驗
- Familiar with TCL/Perl/Python scripting and design automation
5年以上工作經驗
- Experience in 55/40nm design is must, and 28/16nm or below design is a plus
- Experience in FinFet design is must, and whole chip integration is a plus
Tagged as: APR, finfet, physical
